Jack Ou, Ph.D.

Associate Professor, Electrical and Computer Engineering, California State University
Ph,D., M.S., and B.S. Rutgers University (New Brunswick Campus)
Research Interest: CMOS analog/RF integrated circuits

Teaching
Forms and Information Items

  1. Electrical and Engineering Fundamentals Laboratory ECE 240l
  2. Request for Permission Number Form
  3. Prerequisite Check Form
  4. Course Projects (link)
Previously Taught Courses
Electrical and Engineering Fundamentals (ECE 240), Electronics I (ECE 340/L), Electronics II (ECE 440), Digital Electronics (ECE 442), Pulse and Wave-shaping Circuit Design (ECE 443), Senior Design Project (ECE 492/ECE 493), Analog Integrated Circuit Design (ECE 540), RF Electronics Design (ECE 642), Electrical Network Theory (ECE 648), and Active Network Synthesis (ECE 649).

Research
I am interested in the design of ultra power analog and radio frequency integrated circuits. Below is a list of projects that are of interests to me.

  1. Digital based analog circuits.
  2. Low power wake-up receiver (WuRX) circuits.
  3. Design of low power analog neuromorphic circuits.

Selected publications:
1. J. Ou and Ferreira, P., "A Tunable Morris-Lecar Spiking Neuron in CMOS," 2023 IEEE 30th International Midwest Symposium on Circuits and Systems (MWSCAS), Phoenix, AZ, Aug. 6-9, 2023.
2. J. Ou and Ferreira, P., "Analysis of an Inverter-Based CMOS Envelope Detector," 2022 IEEE 29th International Conference on Electronics, Circuits and Systems (ICECS),Glasgow, UK, Oct. 24-26, 2022.
3. J. Ou, "On the Feasibility of an Inverter-Based CMOS Envelope Detector," 2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS).
4. J. Ou, B. Palmer, L. Hou and P. M. Ferreira, "Analysis and Implementation of OVSF Address Decoders," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 1, pp. 80-84, Jan. 2022.
5. Ou, J. and Ferreira, P. "Implications of Small Geometry Effects on Transconductance/Drain Current Based Design Methodology for Analog Circuits," IEEE Transaction of Circuits and Systems II, January, 2019.
6. Ou, J. and Ferreira, P. "A Transconductance/Drain Current Based Noise Optimization for CMOS Folded-Cascode Operational Amplifier," IEEE Transaction of Circuits and Systems II, October, 2014.
7. Ou, J., and Ferreira, P., "A Unified Explanation of Transconductance/Drain Current Based Noise Analysis," Journal of Circuits, Systems and Computers, January, 2015.
8. Caggiano, M.F., Ou, J., Bulumulla, S., Lischner, D., "RF electrical measurements of fine pitch BGA packages," IEEE Transactions on Components and Packaging Technologies, Part A: Packaging Technologies, Volume: 24, Issue: 2, June 2001, Pages: 233-240.
9. Ferreira, P. M., Ou, J., and C. Gaquiere, "Automated System-Level Design for Reliability: RF Front-End Application," Computational Intelligence in Electronic Design, Springer.