ECE 527
Application Specific Integrated Circuit Development
Prerequisite: ECE 526/L or consent of instructor. Well motivated students with a background in that other HDL or those who enroll concurrently in 526 have succeeded in doing well in this course, but working knowledge of Verilog is essential, both for this course and for a professional career in hardware design and development.
ECE 527 covers logic synthesis, timing analysis, creating reliable asynchronous interfaces, a non-theoretical introduction to test and testability and related topics.
Reference the ECE 526 Lab Manual for information on lab report structure. Source code and computer-generated output alone do not constitute even a minimally-acceptable lab report.
Remote login instructions: full version
Remote login instructions: short version
Lab 0: updated Jan. 21
Lab 2 Updated Feb. 5
Setup file data for 90nm Use this library for all synthesis starting with Lab 3.
For simulation, use a path that starts the same as the synthesis setup path but uses "verilog" in place of "synopsys."